This invention relates to an integrated circuit and more particularly to an integrated circuit with a voltage level detector using voltage addition or subtraction.
Present complementary metal oxide semiconductor (CMOS) synchronous dynamic random access memory (SDRAM) circuits are frequently used for main memory m a variety of applications including desk top and portable computer systems. Advances in system technology continually reduce feature sizes and gate dielectric thickness. Internal operating voltages must be closely regulated for these reduced feature sizes and gate dielectric thickness in order to maintain reliability. Moreover, this regulation must be effective over a wide range of external voltage and temperature.
Regulation a internal voltage supplies, such as Vpp and Vbb, for SDRAM and FLASH memory circuits is particularly critical due to the relatively high electric field across the gate dielectric of memory cells during a memory operation. Large variations in voltage supplies Vpp or Vbb may degrade memory cell transistor performance characteristics over time and even lead to dielectric rupture and field failure of SDRAM memory cells. Large variations in voltage supply Vbb may degrade overall circuit performance through transistor threshold voltage variation due to body effect. Previous regulation attempts were based on detecting variation of voltage supplies Vpp and Vbb by an integral number of transistor threshold voltages with respect to supply voltage Vdd or reference voltage Vss. For example, the Vpp level detector circuit of FIG. 9A includes series connected reference transistors 901, 903 and 909 having channel width to length (W/L) ratios of 28/1, 2/5 and 2/5, respectively. These different ratios of reference transistors have a disadvantage of producing reference voltage errors due to transistor threshold voltage variations. The Vbb level detector circuit of FIG. 9B includes series connected P channel reference transistors 951, 953 and 955 and N-channel reference transistors 957 and 959. These reference transistors produce even greater reference voltage errors due to threshold voltage variation, conductivity type and body effect differences arising from different bulk-to-source voltages. These reference voltage errors produce significant variation in regulated levels of voltage supplies such as Vpp or Vbb. Thus, methods of the prior art failed to closely regulate the value of voltage supplies due to a wide variation of transistor threshold voltage with temperature and process parameter variations.
These problems are resolved by a circuit, comprising a first transistor having a current path coupled between a supply terminal and a first output terminal, the first transistor current path having a width and a length. A second transistor has a current path coupled between the first output terminal and a reference terminal and has substantially the same width and length as the first transistor current path. A first comparator circuit has first and second input terminals and a second output terminal. The first input terminal is coupled to the first output terminal. The first comparator circuit produces a control signal in response to a voltage between the first and second input terminals. A generator circuit is coupled to receive the control signal and produces an output voltage at the supply terminal.
The present invention linearly translates the supply voltage to a reference voltage without loss of accuracy due to transistor threshold voltage, temperature or supply voltage variation.